Modern computer systems are often implemented as multiprocessor systems wherein a plurality of processors are coupled to one another by, e.g., a bus. In the operation of the computer system, it is often necessary for the processors to communicate messages to one another. In one known scheme, each message is stored in a buffer by the processor generating the message (the source processor). The source processor then passes a pointer to the buffer to the processor to which the message is directed (the destination processor) and the destination processor utilizes the pointer to read the message from the buffer. As should be understood, each processor can be either a source or destination of messages.
The buffer pointer passing scheme prevents temporary input/output bandwidth crunches at any particular destination processor, as might occur, e.g., if each entire message were directly transmitted to the destination processor and several source processors need to forward messages to the particular destination processor during the same time period. The passing of pointers permits each destination processor to schedule the movement of messages from the appropriate buffers to the respective destination processor. A particular destination processor can readily receive and store pointers and access the associated buffers for the full messages over a time period consistent with the input/output bandwidth of the particular destination processor.
The buffers used to communicate messages can all be arranged in a shared central memory, coupled to the bus. The use of a central memory simplifies the overall design requirements for the buffer system and provides flexibility in the allocation of buffers between processors. At initialization of the system, each source processor is allocated a number of buffers within the central memory consistent with the amount of message traffic expected from that source. In addition, the shared memory can be implemented with an input/output bandwidth at, e.g., twice the peak receive rate for messages so that the central memory can handle the highest possible amount of full message traffic generated throughout the system. In this manner, there are less rigorous bandwidth requirements at each potential destination processor, which, as indicated, need only receive pointers to the buffers storing the full messages and operate to schedule the transfer of the full messages at a rate within the input/output bandwidth of the particular destination processor.
While the known buffer pointer approach to multiprocessor communication provides an advantageous scheme for effectively passing messages between processors, the scheme does not adequately provide for an assured supply of free buffers for each source processor through a reliable return of free buffers by destination processors. This is particularly true in multiprocessor systems with heavy message traffic.